Highly linear low voltage low power CMOS LNA

Kargaran, Ehsan, Zoka, Negar, Kouzani, Abbas Z., Mafinezhad, Khalil and Nabovati, Hooman 2013, Highly linear low voltage low power CMOS LNA, IEICE electronics express, vol. 10, no. 21, pp. 1-6, doi: 10.1587/elex.10.20130557.

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Title Highly linear low voltage low power CMOS LNA
Author(s) Kargaran, Ehsan
Zoka, Negar
Kouzani, Abbas Z.ORCID iD for Kouzani, Abbas Z. orcid.org/0000-0002-6292-1214
Mafinezhad, Khalil
Nabovati, Hooman
Journal name IEICE electronics express
Volume number 10
Issue number 21
Start page 1
End page 6
Total pages 6
Publisher Denshi Jouhou Tsuushin Gakkai (Institute of Electronics Information and Communication Engineers)
Place of publication Tokyo, Japan
Publication date 2013
ISSN 1349-2543
Keyword(s) current reuse
folded cascode
high linear
low noise amplifier (LNA)
low power
low voltage
Summary A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.
Language eng
DOI 10.1587/elex.10.20130557
Field of Research 090604 Microelectronics and Integrated Circuits
090601 Circuits and Systems
Socio Economic Objective 861603 Integrated Circuits and Devices
HERDC Research category C1 Refereed article in a scholarly journal
Copyright notice ©2013, Institute of Electronics Information and Communication Engineer
Persistent URL http://hdl.handle.net/10536/DRO/DU:30060963

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