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Implementation of soft processor based SOC for JPEG compression on FPGA

Swarna, K.S.V. and Raju, Y. David Solomon 2015, Implementation of soft processor based SOC for JPEG compression on FPGA, ICTACT journal on microelectronics, vol. 1, no. 1, pp. 1-7, doi: 10.21917/ijme.2015.0001.

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Title Implementation of soft processor based SOC for JPEG compression on FPGA
Author(s) Swarna, K.S.V.
Raju, Y. David Solomon
Journal name ICTACT journal on microelectronics
Volume number 1
Issue number 1
Start page 1
End page 7
Total pages 7
Publisher I C T Academy of Tamil Nadu
Place of publication Tamil Nadu, India
Publication date 2015-02
ISSN 2395-1680
Keyword(s) prototype
system-on-chip
JPEG compression
micro blaze soft core processor
Summary With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA.
Language eng
DOI 10.21917/ijme.2015.0001
Field of Research 090604 Microelectronics and Integrated Circuits
Socio Economic Objective 970109 Expanding Knowledge in Engineering
HERDC Research category C1 Refereed article in a scholarly journal
ERA Research output type C Journal article
Copyright notice ©2015, I C T Academy of Tamil Nadu
Free to Read? Yes
Use Rights Creative Commons Attribution Non-Commercial Share Alike licence
Persistent URL http://hdl.handle.net/10536/DRO/DU:30081209

Document type: Journal Article
Collections: School of Engineering
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Every reasonable effort has been made to ensure that permission has been obtained for items included in DRO. If you believe that your rights have been infringed by this repository, please contact drosupport@deakin.edu.au.