Implementation of dual stack technique for reducing leakage and dynamic power Swarna, KSV, Raju Y, David Solomon and S, Prasanna 2014, Implementation of dual stack technique for reducing leakage and dynamic power, Global journal of advanced engineering technologies, vol. 3, no. 2, pp. 100-107. Attached Files Name Description MIMEType Size Downloads swarna-implementationof-2014.pdf Published version application/pdf 710.99KB 5 Title Implementation of dual stack technique for reducing leakage and dynamic power Author(s) Swarna, KSV Raju Y, David Solomon S, Prasanna Journal name Global journal of advanced engineering technologies Volume number 3 Issue number 2 Start page 100 End page 107 Total pages 8 Publisher Global Journal of Advanced Engineering Technologies Place of publication Bengaluru, India Publication date 2014 ISSN 2394-0921 2277-6370 Keyword(s) leakage power Dual Stack sub-threshold Summary This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product. Language eng Field of Research 099999 Engineering not elsewhere classified Socio Economic Objective 970109 Expanding Knowledge in Engineering HERDC Research category CN.1 Other journal article ERA Research output type C Journal article Copyright notice ©2014, The Authors Free to Read? Yes Use Rights Persistent URL http://hdl.handle.net/10536/DRO/DU:30081210 Document type: Journal Article Collections: School of Engineering Open Access Collection Related Links Link Description Connect to Elements publication management system Go to link with your DU access privileges   Connect to published version Go to link with your DU access privileges     Unless expressly stated otherwise, the copyright for items in DRO is owned by the author, with all rights reserved. Every reasonable effort has been made to ensure that permission has been obtained for items included in DRO. If you believe that your rights have been infringed by this repository, please contact drosupport@deakin.edu.au. Versions Version Filter Type Sun, 07 Feb 2016, 22:14:37 EST Mon, 08 Feb 2016, 04:00:22 EST Tue, 09 Feb 2016, 07:14:37 EST Wed, 24 Aug 2016, 06:07:31 EST Mon, 12 Dec 2016, 14:42:50 EST Mon, 12 Dec 2016, 14:46:53 EST Mon, 12 Dec 2016, 14:49:56 EST Fri, 28 Jul 2017, 11:03:19 EST Filtered Full Citation counts:   Cited 0 times in TR Web of Science Cited 0 times in Scopus Search Google Scholar Access Statistics: 20 Abstract Views, 7 File Downloads  -  Detailed Statistics Created: Sun, 07 Feb 2016, 22:14:37 EST

Every reasonable effort has been made to ensure that permission has been obtained for items included in DRO. If you believe that your rights have been infringed by this repository, please contact drosupport@deakin.edu.au.