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TC-Release++: an efficient timestamp-based coherence protocol for many-core architectures

Yao, Yuan, Chen, Wenzhi, Mitra, Tulika and Xiang, Yang 2017, TC-Release++: an efficient timestamp-based coherence protocol for many-core architectures, IEEE transactions on parallel and distributed systems, vol. 28, no. 11, pp. 3313-3327, doi: 10.1109/TPDS.2017.2719679.

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Title TC-Release++: an efficient timestamp-based coherence protocol for many-core architectures
Author(s) Yao, Yuan
Chen, Wenzhi
Mitra, Tulika
Xiang, YangORCID iD for Xiang, Yang orcid.org/0000-0001-5252-0831
Journal name IEEE transactions on parallel and distributed systems
Volume number 28
Issue number 11
Start page 3313
End page 3327
Total pages 15
Publisher IEEE
Place of publication Piscataway, N.J.
Publication date 2017-11
ISSN 1045-9219
Keyword(s) cache coherence
many-core architecture
timestamp-based system
memory consistency model
Language eng
DOI 10.1109/TPDS.2017.2719679
Field of Research 0805 Distributed Computing
0803 Computer Software
HERDC Research category C1 Refereed article in a scholarly journal
ERA Research output type C Journal article
Copyright notice ©2017, IEEE
Persistent URL http://hdl.handle.net/10536/DRO/DU:30100376

Document type: Journal Article
Collection: School of Information Technology
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