Block-wise concatenated BCH codes for NAND flash memories

Cho, Sung-gun, Kim, Daesung, Choi, Jinho and Ha, Jeongseok 2014, Block-wise concatenated BCH codes for NAND flash memories, IEEE transactions on communications, vol. 62, no. 4, pp. 1164-1177, doi: 10.1109/TCOMM.2014.021514.130287.

Attached Files
Name Description MIMEType Size Downloads

Title Block-wise concatenated BCH codes for NAND flash memories
Author(s) Cho, Sung-gun
Kim, Daesung
Choi, JinhoORCID iD for Choi, Jinho orcid.org/0000-0002-4895-6680
Ha, Jeongseok
Journal name IEEE transactions on communications
Volume number 62
Issue number 4
Start page 1164
End page 1177
Total pages 14
Publisher IEEE
Place of publication Piscataway, N.J.
Publication date 2014-04
ISSN 0090-6778
Keyword(s) Science & Technology
Technology
Engineering, Electrical & Electronic
Telecommunications
Engineering
Error-correcting codes
storage systems
NAND flash memories
concatenated codes
TO-CELL INTERFERENCE
CYCLIC PRODUCT CODES
LDPC CODES
ERROR-CORRECTION
ARCHITECTURE
ALGORITHMS
DECODER
Language eng
DOI 10.1109/TCOMM.2014.021514.130287
Field of Research 0906 Electrical And Electronic Engineering
1005 Communications Technologies
HERDC Research category C1.1 Refereed article in a scholarly journal
Copyright notice ©2014, IEEE
Persistent URL http://hdl.handle.net/10536/DRO/DU:30114634

Connect to link resolver
 
Unless expressly stated otherwise, the copyright for items in DRO is owned by the author, with all rights reserved.

Versions
Version Filter Type
Citation counts: TR Web of Science Citation Count  Cited 22 times in TR Web of Science
Scopus Citation Count Cited 27 times in Scopus
Google Scholar Search Google Scholar
Access Statistics: 61 Abstract Views, 0 File Downloads  -  Detailed Statistics
Created: Fri, 26 Oct 2018, 13:56:39 EST

Every reasonable effort has been made to ensure that permission has been obtained for items included in DRO. If you believe that your rights have been infringed by this repository, please contact drosupport@deakin.edu.au.