Design and implementation of a hybrid single T-type double H-bridge multilevel inverter (STDH-MLI) topology

Rawa, Muhyaddin, Siddique, Marif Daula, Mekhilef, Saad, Shah, Noraisyah Mohamed, Bassi, Hussain, Seyedmahmoudian, Mohammadmehdi, Horan, Ben and Stojcevski, Alex 2019, Design and implementation of a hybrid single T-type double H-bridge multilevel inverter (STDH-MLI) topology, Energies, vol. 12, no. 9, pp. 1-15, doi: 10.3390/en12091810.

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Title Design and implementation of a hybrid single T-type double H-bridge multilevel inverter (STDH-MLI) topology
Author(s) Rawa, Muhyaddin
Siddique, Marif Daula
Mekhilef, Saad
Shah, Noraisyah Mohamed
Bassi, Hussain
Seyedmahmoudian, Mohammadmehdi
Horan, BenORCID iD for Horan, Ben
Stojcevski, Alex
Journal name Energies
Volume number 12
Issue number 9
Article ID 1810
Start page 1
End page 15
Total pages 15
Publisher MDPI
Place of publication Basel, Switzerland
Publication date 2019-05
ISSN 1996-1073
Keyword(s) H-bridge
hybrid inverter
multilevel inverter
nearest level control
pulse width modulation (PWM)
reduced switch count
Science & Technology
Energy & Fuels
Summary Multilevel inverters are proficient in achieving a high-quality staircase output voltage waveform with a lower amount of harmonic content. In this paper, a new hybrid multilevel inverter topology based on the T-type and H-bridge module is presented. The proposed topology aims to achieve a higher number of levels utilizing a lower number of switches, direct current (dc) voltage sources, and voltage stresses across different switches. The basic unit of the proposed single T-type and double H-bridge multilevel inverter (STDH-MLI) produces 15 levels at the output using three dc voltage sources. The proposed topology can be extended by connecting a larger number of dc voltage sources in the T-type section. The nearest level control (NLC) switching technique is used to generate gate pulses for switches to achieve a high-quality output voltage waveform. In addition, a simplified way to achieve NLC is also described in the paper. A detailed comparison with other similar topologies is provided to set the benchmark of the proposed topology. Finally, experimental work is carried out to validate the performance of the proposed topology.
Language eng
DOI 10.3390/en12091810
Field of Research 09 Engineering
02 Physical Sciences
HERDC Research category C1 Refereed article in a scholarly journal
ERA Research output type C Journal article
Copyright notice ©2019, the authors
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