Asymmetrical multilevel inverter topology with reduced number of components

A new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.