A 60-GHz OOK receiver with an on-chip antenna in 90 nm CMOS

A low power 60-GHz on-off-keying (OOK) receiver has been implemented in a commercial 90 nm RF CMOS process. By employing a novel on-chip antenna together with architecture optimization, the receiver achieves a sensitivity of -47 dBm at a bit-error rate (BER) of less than 10 -3 . Using a commercial transmitter with transmit power of 1.5 dBm, a transmission distance of 5 cm can be achieved at 1.2 Gbps data rate. In this design, the on-chip antenna minimizes the packaging loss, while energy detection at RF allows architecture simplification. Both techniques contribute to the receiver's low power consumption of 51 mW, excluding test buffers. This leads to a bit energy efficiency of 28 pj/bit at 1.8 Gbps. The total die area is 3.8 mm 2 with the on-chip antenna occupying almost half of it.