A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.