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Fast fault tree analysis for hybrid uncertainties using stochastic logic implemented on field-programmable gate arrays: an application in quantitative assessment and mitigation of welding defects risk

Version 2 2024-06-04, 12:09
Version 1 2018-02-22, 13:02
journal contribution
posted on 2024-06-04, 12:09 authored by S Shoar, HR Zarandi, Farnad NasirzadehFarnad Nasirzadeh, E Cheshmikhani
This paper presents a stochastic logic-based method for quantitative risk assessment using fault tree analysis (FTA) that can take into account both types of uncertainties including objective and subjective uncertainties. In the proposed method, each fault tree gate is translated to its corresponding stochastic logic template and then is implemented on a field programmable gate array (FPGA). Because the analysis does not utilize any transformation methods, the results of analysis are more accurate than those methods which are based on transformation from possibility to probability distributions or vice versa. Experimental results for a benchmark fault tree show that this method accelerates analysis time compared to conventional hybrid uncertainty analysis method and transformation methods. The efficiency of the proposed method is demonstrated by implementation in a real steel structure project. The quantitative risk assessment is performed for the incomplete penetration as one of the defects encountered in arc welding process, and its results are compared with transformation methods. The comparison results show the proposed hybrid uncertainty analysis method is also more accurate in comparison to the transformation-based approaches.

History

Journal

Quality and reliability engineering international

Volume

33

Pagination

1367-1385

Location

Chichester, Eng.

ISSN

0748-8017

Language

eng

Publication classification

C Journal article, C1.1 Refereed article in a scholarly journal

Copyright notice

2016, John Wiley & Sons, Ltd.

Issue

7

Publisher

John Wiley & Sons