kouzani-highlylinear-2013.pdf (1.18 MB)
Highly linear low voltage low power CMOS LNA
journal contribution
posted on 2013-01-01, 00:00 authored by E Kargaran, N Zoka, Abbas KouzaniAbbas Kouzani, K Mafinezhad, H NabovatiA highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.
History
Journal
IEICE electronics expressVolume
10Issue
21Pagination
1 - 6Publisher
Denshi Jouhou Tsuushin Gakkai (Institute of Electronics Information and Communication Engineers)Location
Tokyo, JapanPublisher DOI
Link to full text
ISSN
1349-2543eISSN
1349-9467Language
engPublication classification
C1 Refereed article in a scholarly journalCopyright notice
2013, Institute of Electronics Information and Communication EngineerUsage metrics
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