Deakin University
Browse
swarna-implementationof-2014.pdf (711 kB)

Implementation of dual stack technique for reducing leakage and dynamic power

Download (711 kB)
journal contribution
posted on 2014-01-01, 00:00 authored by Swarna Kumary Srungarakavi Venkata, D S Raju Y, Prasanna S
This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. The
combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on
a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become an
increasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases as
technology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product when
compared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses the
advantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.
The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speed
power product.

History

Journal

Global journal of advanced engineering technologies

Volume

3

Issue

2

Pagination

100 - 107

Publisher

Global Journal of Advanced Engineering Technologies

Location

Bengaluru, India

ISSN

2394-0921

eISSN

2277-6370

Language

eng

Publication classification

C Journal article; CN.1 Other journal article

Copyright notice

2014, The Authors

Usage metrics

    Research Publications

    Categories

    No categories selected

    Exports

    RefWorks
    BibTeX
    Ref. manager
    Endnote
    DataCite
    NLM
    DC