Low-noise and small-area integrated amplifier circuit for mems-based implantable hearing aid applications

Hearing aid devices are used by patients with hearing impairment to help with hearing problems. These devices consist of a microphone, an amplifier, and speaker modules. The author previously developed a micro-electromechanical piezoelectric diaphragm for a hearing aid device. The proposed diaphragm was in circular shape with 700 μm diameter and 10 μm thickness using AlN piezoelectric material. The design was performed in MEMS scale to offer maximum performance by the diaphragm for the human hearing frequency range. Adding to the previous work, in the present paper, a voltage amplifier circuit is designed for that piezoelectric microphone. The design is performed with respect to suitable circuit performance for the 5 Hz–22.5 kHz frequency range, small area, low noise, high gain and integration capability between the circuit and the diaphragm. The designed circuit is modeled and implemented in Cadence based on the 180 nm (0.18 μm) CMOS technology standard and the circuit layout is demonstrated with the circuit occupying an area of 0.08 mm × 0.04 mm. Simulation study is performed for assessment of the performance of the circuit. The results indicate that the frequency range of the amplifier covers the audio frequency of 5 Hz–22.5 k Hz, the amplification gain is 84.78 dB with the phase margine (PM) of 75.95°, the average power consumption of 0.216 mW, the Input noise level of 4.19 μVrms, CMRR of 133.69 dB and PSRR of 98.76 dB. The integration of the circuit with the microphone for hearing aid devices is proposed based on circuit binding method.