- No file added yet -

Resource-constrained FPGA/DNN co-design

Version 2 2024-06-04, 00:19

Version 1 2021-05-26, 15:23

journal contribution

posted on 2024-06-04, 00:19 authored by Z Zhang, Abbas KouzaniAbbas Kouzani

Resource-constrained FPGA/DNN co-design

History

Journal

Neural Computing and Applications

Volume

33

Pagination

14741-14751

Location

England

Publisher DOI

https://doi.org/10.1007/s00521-021-06113-4

Open access

Yes

Link to full text

https://link.springer.com/content/pdf/10.1007/s00521-021-06113-4.pdf

ISSN

0941-0643

eISSN

1433-3058

Language

English

Author URL

http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000650841100001&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=a045e4b2bb1f2b747c68c720ec8913b7

Publication classification

C1 Refereed article in a scholarly journal

Issue

21

Publisher

SPRINGER LONDON LTD

Usage metrics

Categories

Keywords

Science & Technology Technology Computer Science, Artificial Intelligence Computer Science Lempel-Ziv-Welch compression Deep neural network Hardware-and-software co-design Electrochemical sensing Field-programmable gate array DEEP NEURAL-NETWORKS MODEL 4009 Electronics, sensors and digital hardware

Licence

All Rights Reserved

Exports

RefWorks

BibTeX

Ref. manager

Endnote

DataCite

NLM

DC