SRAM precharge system for reducing write power

This paper presents the static random access memory (SRAM) precharge system by using an equaliser and a sense circuit. Recent goals of designing SRAM are to reduce area, delay, and power, and to maintain standard data stability and writability. By using an equaliser, column select and a sense circuit, precharging the bit-lines at Vdd-Vtp was successful. As charge is mostly shared during precharge and lower voltage swing occurs, dynamic power is lower. The performance of the proposed SRAM is analysed and compared with that of conventional SRAM. The write power of SRAM is reduced by 39.17% compared to conventional SRAM, when maintaining other parameters are almost the same.